In semiconductor devices such as RapidChip™ developed by LSI Logic Corp., and FPGAs (Field Programmable Gate Arrays), it is often desired to provide flexibility to change the size of a memory and also reduce the overall test cost of the memory without adding significant performance penalty and area. Conventionally, this is performed using external muxing (i.e., multiplexing) in standard cells. However, there is no scheme available to reduce the test overhead. In addition, external muxing in standard cells is not acceptable because it takes a significant area and causes significant performance penalty. Moreover, the cost of BIST (Built-In Self-Test) per memory is also significant because the memory sizes themselves are kept very small and wide to support a wide range of configurations. This also creates an inefficient test organization and implementation.
Thus, it is desirable to have a method and apparatus to provide flexibility in memories and also reduce the overall test cost without adding significant performance penalty and area.